This invention relates to semiconductor memory devices and methods of manufacture, and more particularly to a one-transistor dynamic read/write memory of the N-channel silicon gate type.
Dynamic read/write memory cells made by the double-level polysilicon N-channel self-alligned process commonly used in the industry are shown in pending U.S. Pat. No. 4,240,092 by C-K Kuo, assigned to Texas Instruments, as well as in Electronics, Feb. 19, 1976, pp. 116-121, May 13, 1976, pp. 81-86, and Sept. 28, 1978, pp. 109-116.
In prior cells, the "bit" lines (Y or column input/output lines) are formed of N+ diffused silicon, or in some cases of polysilicon strips. The series resistance of bit lines formed of diffused silicon or poly can become a problem in large arrays, especially as the sizes are scaled down for maximum density. It would be preferable to use aluminum for the bit lines due to its higher conductivity. However, the space needed for metal-to-silicon contacts results in large cell sizes when metal bit lines are employed. The N+ "moat" area heretofore has been made much larger than the contact area to allow for missallignment tolerance of the contact hole; metal must not touch the edge of the moat because of leakage caused by such a condition.
Another problem in prior dynamic memory cells is errors induced by ambient alpha particles. Storage capacitors can be discharged by this radiation.
It is the principal object of this invention to provide an improved dynamic read/write memory. Another object is to provide a dynamic memory of reduced cell size. An additional object is to provide a dense array of memory cells, made by a more efficient method. A further object is to provide an improved way of making metal-to-silicon contacts in memory cells. Another object is to provide alpha particle protection in memory cells.